Electronic chips, for example a system on a chip (SOC), require dc power distribution for proper functioning. DC power distribution on an electronic chip may employ a pre-defined power grid (PG) architecture for each design prior to the place and route step in manufacturing. The place and route step is the process by which individual chip elements are positioned within the chip and interconnected to form a functioning circuit system. Conventionally, a uniform power grid architecture may be assigned to the entire circuit system. The uniform power grid architecture may include an array of vertical conductive lines and horizontal conductive lines. This architecture may limit design optimization with respect to routability (i.e., ability to interconnect elements) and voltage drop (e.g, IR drop with I=current and R=resistance) due to line resistance. Conventionally, to address a local routability issue, the entire power grid must be redesigned. Similarly, in the conventional method, to address local voltage drop issues, the entire power grid must be redesigned. Hence, a local routability issue or a local voltage drop issue is addressed at the entire power grid in a global manner which can adversely affect optimization for the rest of the power grid elements.